This invention relates to control of the generation of data displays, and in particular to a technique which is especially effective when applied to a control device employed for the display of digital image data, for example, in a cathode ray tube (CRT) display device.
In order to cause a CRT display device to display image data which has been previously written in a memory by a computer or the like, for example, it is necessary to access the memory to read out this image data and to prepare synchronizing signals corresponding to the access period. If a sequence of these processing operations are assigned, for instance, to a CPU (central processing unit) of a computer system, the tasks of the CPU are increased, and thus the entire throughput thereof is greatly reduced. Display control devices which are exclusively used for executing these processing operations separately, namely the control of the memory and the preparation of synchronizing signals, have been proposed previously by the inventors and are embodied in display control device Models HD6845, HD68A45 and HD6845S of Hitachi, Ltd.
These display control devices are also called CRTCs. Each of these devices is provided with a scanning counter which is incremented at a period based on the timing of access to the memory, whose count is circulated periodically, and which has functions such that the memory can be accessed according to address data prepared on the basis of the count of the scanning counter and a horizontal synchronizing signal and a vertical synchronizing signal can each be generated based on the count of the scanning counter, so that image data stored in the memory can be displayed on a display device of a scanning system in which an image display screen is formed of horizontal scanning lines forming successive frames. Such a CRTC is formed of a semiconductor integrated circuit, and it is typically connected as a peripheral device to a system bus of a CPU, for example, when in use. This relieves the CPU of the task of display control, in terms of both hardware and software, and thus the throughput of the entire system can be increased.
The present inventors have examined a method in which, when a plurality of these CRTCs are used, image data stored in memories controlled by each of the CRTCs is superposed and displayed on one image display screen. The inventors have found, however, that it is insufficient to simply apply the same basic clock to each CRTC to provide a superposed display on one image screen. In a CRTC, horizontal and vertical synchronizing signals are generated to control the CRT display device. These synchronizing signals are generated by the scanning counter which counts a basic clock provided from the external equipment. Here, when a plurality of CRTCs each generate identical synchronizing signals based on the same basic clock, the phases of these synchronizing signals do not always agree with each other. For example, once the count of the scanning counter in any one of the CRTCs differs from those in the other CRTCs, this difference appears as a phase difference between the synchronizing signals, and this state is not automatically corrected, but remains. As a result, the positional relationships of the superposed images, or the synchronization thereof, is disrupted.